This invention relates, in general, to a method of making an electronic device, and more particularly, to a method of fabricating a flip chip semiconductor device having an integrated inductor.
With the expanding portable communications market, many products operate in the rf or radio frequency ranges. Integrated circuits operating in these high frequency ranges require passive components including inductors and capacitors for impedance matching, capacitive coupling, filtering, and tuning. In addition to the passive components, flip chip bumps are used for improving high frequency performance over conventional wire bonded semiconductor chips.
An integration scheme for flip chip bumps and inductors involves sputtering a seed layer comprising titanium tungsten and copper onto a substrate, using a first photoresist pattern to define inductors on the seed layer, and electroplating copper onto the exposed portions of the seed layer to form the inductors. After removal of the first photoresist pattern, a second photoresist pattern is used to cover the inductors and to define flip chip bumps on the seed layer. Copper is subsequently electroplated onto the exposed portions of the seed layer to form the copper stud portion of the flip chip bumps. Lead is electroplated onto the copper of the flip chip bump; tin is electroplated onto the lead; and finally, the second photoresist pattern is removed.
To eliminate shorting of the inductors and the flip chip bumps by the seed layer, the portion of the seed layer not used to define the inductors or flip chip bumps must now be removed. It is this removal process which introduces manufacturing issues into the integration scheme.
When a commercially available etchant such as MacDermit Metex FA/Metex FB is used to etch the exposed sputtered copper of the seed layer, the electroplated copper inductors are etched even more aggressively due to the approximate 5:1 etch selectivity of Metex FA/Metex FB for electroplated and sputtered copper. The aggressive etching of the electroplated copper inductor changes its inductance and detrimentally affects the high frequency performance of the integrated device. To improve the etch selectivity, ammonium peroxydisulfate is used to reduce the etch rate of the electroplated copper while increasing the etch rate of the sputtered copper. However, ammonium peroxydisulfate also aggressively etches tin which degrades the flip chip bump. The lead tin cap covering the copper stud of the flip chip bump is required for bonding of the semiconductor device to a substrate.
The sputtered copper seed layer can be etched prior to the lead and tin plating to eliminate the problem of ammonium peroxydisulfate etching the tin cap of the flip chip bump. However, the second photoresist pattern must first be removed prior to etching the sputtered copper seed layer. Additionally, after the etch, a third photoresist pattern must be developed to the precise alignment of the second layer. The extremely small alignment tolerance of the third layer of photoresist is crucial for proper fabrication of flip chip bumps. Consequently, the alignment process is quite difficult and increases the fabrication process cycle time due to the additional photoresist step.
Accordingly, a need exists for fabricating a flip chip semiconductor device having integrated inductors. The fabrication method should not significantly degrade the inductors or the flip chip bumps and should not significantly increase process cycle time.